SEOUL — Every chip Samsung wants to build at 1nm or below runs into the same problem. The circuit patterns that need to be printed onto silicon are so fine, and light so imprecise, that simply predicting how those patterns will distort has become a computational problem serious enough to slow the entire process down. The company has been trying to fix this for more than a decade with classical computers. Now its IT services affiliate is experimenting with something different.
Samsung SDS – the Samsung Group’s system integration arm – disclosed this week that it has joined the internal semiconductor research effort to develop quantum computing algorithms for optical proximity correction, the simulation step that predicts and corrects light distortion before chip patterns are etched onto a wafer. The proof of concept is scheduled for the second half of this year, according to the Seoul Economic Daily, which first reported the effort.
The problem Samsung is trying to solve with quantum computing is specific, unglamorous, and genuinely hard. OPC is not the photolithography itself – it is the mathematical preparation that makes photolithography possible. Before any circuit is printed, engineers must calculate how extreme ultraviolet light will behave as it passes through lenses and masks at near-atomic scales, and pre-correct the design so that what ends up on the wafer matches what was intended. In older processes, two or three variables dominated those calculations. At the angstrom scale – the 1nm class of chips Samsung is chasing – at least 20 conditions must be calculated simultaneously. Classical computers can do it, but the time and cost compound across millions of wafers a year.
Samsung’s proposed fix is a hybrid: a quantum processor handles the core simulation mathematics, a classical computer handles post-processing, and an AI layer detects and corrects errors introduced by the quantum hardware in real time. The structure reflects where quantum computing actually stands right now – useful for specific, structured optimization problems when paired with classical systems, but not ready to replace them. Samsung’s semiconductor R&D center has worked on OPC independently for more than a decade; Samsung SDS joining the effort signals the problem has grown large enough to require a different kind of computational infrastructure.
This is not a product announcement. Samsung SDS has been explicit that it does not plan to commercialize the technology as standalone software – if the proof of concept succeeds, the results go to Samsung Electronics’ Semiconductor Research Center, not to market. What Samsung gets, if it works, is a manufacturing edge it cannot currently buy from any software vendor or compute cluster upgrade.
That matters because of where Samsung stands in the foundry race. Taiwan Semiconductor Manufacturing Company remains the dominant advanced-node chipmaker; virtually every major AI chip – including the Nvidia processors at the center of the AI governance conversation Jensen Huang joined this week – is built at TSMC. Samsung has been competing at the leading edge for years, but its yield rates at the most advanced nodes have consistently lagged. Yield – the percentage of chips on a wafer that actually work – is the variable that makes or breaks a foundry’s economics. A process that improves how accurately circuit patterns are printed directly improves yield.
Quantum computing has been on Samsung’s agenda for some time: both Samsung Electronics and Samsung SDS have separate quantum research groups, and Samsung SDS earlier developed domestic post-quantum cryptography standards. But applying quantum hardware to the core manufacturing simulation of semiconductor fabrication – rather than to security or software problems – is a different kind of bet. It requires the quantum system to perform reliably at industrial scale rather than demonstrating capability in a controlled research environment.
Whether the proof of concept will succeed is the question Samsung cannot answer yet. The company has not disclosed which quantum hardware platform Samsung SDS is using for the OPC simulation, how many qubits the system requires, or what error rates it is targeting. These are not minor technical details – the gap between what quantum hardware can do in a laboratory and what it needs to do to improve a real production line remains significant. The AI error-correction layer in Samsung’s hybrid architecture is, in part, a tacit acknowledgment of that gap: quantum computers make errors, and the system has to catch them in real time or the simulation output becomes unreliable.
Samsung is not alone in pursuing quantum-classical hybrids for industrial simulation. IBM, Google, and a number of startups have positioned similar architectures as the near-term path to practical quantum utility. What is unusual about Samsung’s application is the domain: chip lithography simulation requires deep integration with proprietary manufacturing data that only Samsung has access to. If the POC succeeds, Samsung would have a capability that competitors cannot replicate by buying time on a quantum cloud service or licensing a software tool.
The chip that Samsung wants to eventually build with this technology – at the angstrom scale, at 1nm and below – is still four years from mass production targets. That is a long runway, and also a sign of how early Samsung is placing this bet. The second-half 2026 proof-of-concept deadline Samsung SDS has set for itself is not a product ship date. It is the moment when the company will find out whether the quantum-classical-AI hybrid can handle even a controlled simulation of the problem at the scale the production line actually presents. What happens after that, if the POC works, is not yet decided.
