NEW YORK – For decades, the semiconductor industry has confronted the same arithmetic: transistors can only shrink so far before the physics of silicon stops cooperating. On Thursday, IBM said it had found a way around the physics.
The company unveiled what it described as the world’s first sub-1 nanometer chip technology, a transistor architecture called nanostack operating at the 0.7 nanometer, or 7-angstrom, node. The chip packs nearly 100 billion transistors onto a surface the size of a fingernail, IBM said in its announcement – roughly twice the density of IBM’s 2-nanometer chip from 2021, itself only now approaching volume production.
Instead of continuing to shrink two-dimensional transistors, the nanostack approach stacks them vertically in three-dimensional layers using a process called 3D sequential integration. IBM builds one complete layer of transistors before constructing the next layer above it, with pairs slightly staggered rather than directly aligned.
The transistors themselves use nanosheets as the channel material: three stacked sheets, each approximately 15 atoms thick, spaced nine nanometers apart. The design allows IBM to use different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independently.
The result, IBM says, is up to 50 percent more computational performance or up to 70 percent greater energy efficiency compared with its 2-nanometer chips, along with a 40 percent improvement in on-chip SRAM memory density, MIT Technology Review reported.
The SRAM improvement is arguably as significant as the transistor count. AI inference workloads require constant, high-speed access to model weights stored in on-chip memory; the more SRAM a chip can pack per unit area, the less data needs to travel across slower, more power-hungry external memory pathways.
A 40 percent SRAM density improvement is a level of memory scaling the industry has not seen in more than a decade. For the companies now building custom inference chips designed specifically to reduce data-movement costs, a node that delivers better memory density on top of raw compute gains is a compounding advantage, not just an incremental one.
IBM has not published a full transistor-level performance breakdown for specific AI workloads. The 50 percent performance and 70 percent efficiency figures compare nanostack with the 2nm node architecture in general compute terms, not benchmarks tailored to transformer model inference.
IBM’s semiconductor research history follows a consistent pattern: major architecture announcements followed by long timelines to commercial production through foundry partners. The company no longer operates high-volume logic fabs; it licenses its architectures to Samsung, TSMC, and Intel, which manufacture chips based on IBM’s research at scale.
IBM’s 2-nanometer chip was unveiled in May 2021. Five years later, it is only now approaching the early stages of volume production. The nanostack announcement carries a matching five-year production estimate, meaning the commercial timeline extends to approximately 2031, according to IEEE Spectrum’s technical analysis.
The research has been experimentally validated through ultra-thin dielectric bonding in CMOS integration, a functional CMOS inverter, and switching behavior at expected performance levels. The physics works. Whether it works economically at foundry volume is a separate question that half a decade of engineering will need to answer.
The energy efficiency claim is the reason the announcement drew attention beyond the chip engineering community. AI data centers are consuming electricity at a pace that has begun colliding with national grid capacity in the United States, Europe, and parts of Asia. A chip that delivers the same computational output for 70 percent less energy is not a product improvement: it is potential relief for a supply constraint now limiting where AI infrastructure can be built.
The pressure runs through the entire compute stack. Apple and Microsoft raised consumer device prices this month, in part because AI memory demand pushed DRAM prices up nearly 100 percent since the start of 2026. The underlying dynamic is the same: more AI compute is being demanded faster than the energy and silicon economics that support it can expand.
The nanostack’s efficiency gains, if they hold at production scale, would not arrive for years. But the semiconductor baseline being set in research today determines what becomes available to build data centers with in 2030 and beyond.
The original formulation of Moore’s Law predicted that transistor counts would double roughly every two years. That specific mechanism effectively ended as a physical reality somewhere around the 5nm node, when the economics of shrinking flat transistors became increasingly unfavorable. What IBM’s nanostack demonstrates is that density can still grow, through vertical stacking rather than horizontal shrinking.
That is a materially different physical mechanism requiring different manufacturing processes, different materials science, and a different industrial supply chain than the one the foundry industry has spent 50 years building. Samsung is IBM’s closest manufacturing partner and the most likely first foundry to attempt nanostack at production scale.
Whether this constitutes an extension of Moore’s Law or its replacement with something new is partly semantic. The practical outcome, if nanostack reaches production scale on anything close to its announced timeline, is that the relationship between chip area and computational capacity continues improving for at least another decade. For the AI industry, where demand for more efficient compute is outpacing what current nodes can supply, that timeline is what the announcement is really about.
